SI4713-B30-GMR【PDF 23/42 页】IC TX FM RADIO RPS/RDS 20UQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录57

19页 20页 21页 22页 [23页]24页 25页 26页 27页

Si4712/13-B30

Rev. 1.1

5.4. Digital Audio Interface

The digital audio interface operates in slave mode and

supports 3 different audio data formats:

1. I

2. Left-Justified

3. DSP Mode

5.4.1. Audio Data Formats

In I

S mode, the MSB is captured on the second rising

edge of DCLK following each DFS transition. The

remaining bits of the word are sent in order, down to the

LSB. The Left Channel is transferred first when the DFS

is low, and the Right Channel is transferred when the

DFS is high.

In Left-Justified mode, the MSB is captured on the first

rising edge of DCLK following each DFS transition. The

remaining bits of the word are sent in order, down to the

LSB. The Left Channel is transferred first when the DFS

is high, and the Right Channel is transferred when the

DFS is low.

In DSP mode, the DFS becomes a pulse with a width of

1 DCLK period. The Left Channel is transferred first,

followed right away by the Right Channel. There are two

options in transferring the digital audio data in DSP

mode: the MSB of the left channel can be transferred on

the first rising edge of DCLK following the DFS pulse or

on the second rising edge.

In all audio formats, depending on the word size, DCLK

frequency and sample rates, there may be unused

DCLK cycles after the LSB of each word before the next

DFS transition and MSB of the next word.

The number of audio bits can be configured for 8, 16,

20, or 24 bits.

5.4.2. Audio Sample Rates

The device supports a number of industry-standard

sampling rates including 32, 40, 44.1, and 48 kHz. The

digital audio interface enables low-power operation by

eliminating the need for redundant DACs and ADCs on

the audio baseband processor. The sampling rate is

selected using the DIGITAL_INPUT_SAMPLE_RATE

property.

The device supports DCLK frequencies above 1 MHz.

After powerup the DIGITAL_INPUT_SAMPLE_RATE

property defaults to 0 (disabled). After DCLK is

supplied, the DIGITAL_INPUT_SAMPLE_RATE

property should be set to the desired audio sample rate

such as 32, 40, 44.1, or 48 kHz. The

DIGITAL_INPUT_SAMPLE_RATE property must be set

to 0 before DCLK is removed or the DCLK frequency

drops below 1 MHz. A device reset is required if this

requirement is not followed.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式